The present invention is related in general to the field of semiconductor devices and processes, and more specifically to assembly methods for integrated circuit chips resulting in multichip devices in a single package, having advanced performance characteristics yet fast turn-around development times.
It is advantageous for many applications of semiconductor devices to arrange the needed devices in close proximity, even in a cluster. When only two, or few more, semiconductor chips are needed, various arrangements have been proposed in order to achieve the desired proximity, and to enable a minimization of required space. Typically, these arrangements are assemblies of semiconductor chips on a substrate, with or without a specific encapsulation. For these arrangements, the term xe2x80x9cmultichip modulexe2x80x9d is commonly used. For an encapsulated assembly, the term xe2x80x9cmultichip packagexe2x80x9d has been introduced. For many years, there has been a rather limited market for multichip modules and multichip packages, but driven by the rapidly expanding penetration of integrated circuit applications, this market is recently growing significantly in size. In order to participate in this market, though, the multichip products have to meet several conditions.
The multichip product has to offer the customer performance characteristics not available in single-chip products. This means, the multichip product has to leapfrog the development of single-chip product.
The multichip product has to be available to the customer at short notice. This means, the multichip product should use readily available components and fabrication methods.
The multichip product has to offer the customer a cost advantage. This means, the design and fabrication of the multichip product has to avoid unconventional or additional process steps.
The multichip product has to offer low cost-of-ownership. This means, it has to operate reliably based on built-in reliability.
Numerous multichip packages have been described in publications and patents. For instance, U.S. Pat. No. 4,862,322, Aug. 29, 1989 (Bickford et al.) entitled xe2x80x9cDouble Electronic Device Structure having Beam Leads Solderlessly Bonded between Contact Locations on each Device and Projecting Outwardly from Therebetweenxe2x80x9d describes a structure of two chips facing each other, in which the input/output terminals are bonded by beam leads. The high cost, however, of materials, processing and controls never allowed the beam lead technology to become a mainstream fabrication method.
In U.S. Pat. No. 5,331,235, Jul. 19, 1994 (H. S. Chun) entitled xe2x80x9cMulti-Chip Semiconductor Packagexe2x80x9d, tape-automated bonding plastic tapes are used to interconnect two chips of identical types, facing each other, into pairs. One or more of these pairs are then assembled into an encapsulating package, in which the plastic tapes are connected to metallic leads reaching outside of the package to form the leads or pins for surface mount and board attach. The high cost of the plastic tapes and the lack of batch processing kept the technology of tape-automated bonding at the margins of the semiconductor production.
Several proposals have been made of multichip devices in which two or more chips are arranged side by side, attached to a supporting substrate or to leadframe pads. An in example is U.S. Pat. No. 5,352,632, Oct. 4, 1994 (H. Sawaya) entitled xe2x80x9cMultichip Packaged Semiconductor Device and Method for Manufacturing the Samexe2x80x9d. The chips, usually of different types, are first interconnected by flexible resin tapes and then sealed into a resin package. The tapes are attached to metallic leads which also protrude from the package for conventional surface mounting. Another example is U.S. Pat. No. 5,373,188, Dec. 13, 1994 (Michii et al.) entitled xe2x80x9cPackaged Semiconductor Device including Multiple Semiconductor Chips and Cross-over Leadxe2x80x9d. The chips, usually of different types, are attached to leadframe chip pads; their input/output terminals are wire bonded to the inner lead of the leadframe. In addition, other leads are used under or over the semiconductor chips in order to interconnect terminals which cannot be reached by long-spanned wire bonding. Finally, the assembly is encapsulated in a plastic package. In both of these examples, the end products are large, since the chips are placed side by side. In contrast today""s applications require ever shrinking semiconductor product, and board consumption is to be minimized.
U.S. Pat. No. 5,438,224, Aug. 1, 1995 (Papageorge et al.) entitled xe2x80x9cIntegrated Circuit Package having a Face-to-Face IC Chip Arrangementxe2x80x9d discloses an integrated circuit (IC) package with a stacked IC chip arrangement placed on a circuit substrate. Two chips are positioned face to face, with a substrate made of tape-automated bonding tape or flex circuit interposed between the chips to provide electrical connection among the terminals of the flip chip and external circuitry; a separate mechanical support is needed for the assembly. In addition to this cost, fabrication is difficult due to the lack of rigid support for the chips.
U.S. Pat. No. 5,770,480, Jun. 23, 1998 (Ma et al.) entitled xe2x80x9cMethod of Leads between Chips Assemblyxe2x80x9d increases the IC density by teaching the use of leadframe fingers to attach to the bond pads of multiple chips employing solder or conductive bumps. While in the preferred embodiments both chips of a set are identical in function, the method extends also to chips with differing bond pad arrangements. In this case, however, the leadframe needs customized configuration and non-uniform lengths of the lead fingers, especially since the use of bond wires is excluded. The manufacture of these so-called variable-leads-between-chips involves costly leadframe fabrication equipment and techniques. In addition, a passivation layer is required, to be disposed between the two chips and the customized lead fingers, in order to prevent potential electrical shorts, adding more material and processing costs.
An urgent need has therefore arisen for a coherent, low-cost method of fabricating multichip packages based on available chip designs and assembly and encapsulation techniques. The method should be flexible enough to be applied for different semiconductor product families and a wide spectrum of design and process variations, should add no additional cost to the existing fabrication methods, and deliver high-quality and high-reliability products. Preferably, these innovations should be accomplished while shortening production cycle time and increasing throughput.
The present innovation provides a method for increasing integrated circuit density and creating novel performance characteristics. The multichip device comprises a stack of typically two semiconductor chips with a leadframe including a plurality of leads disposed between the chips. The device is produced by connecting each of the chip contact pads to one of the leads, respectively, whereby the connections to at least one of the leads are common between the first and second chips. The interconnection method may be wire bonding or solder reflow, whatever the designs of the chips-to-be-connected require.
The chips of the stack can be found in many semiconductor device families; preferred embodiments of the invention include chip pairs of dynamic random-access memories (DRAMs) and static random-access memories (SRAMs), FLASH memories and SRAMs, digital signal processors (DSPs) and SRAMs, and application-specific integrated circuits (ASICs) and SRAMs. In these examples, each chip of the stacks is readily available. If one would endeavor to duplicate the performance of the stacked chips by a single chip, it would not only require precious design and development time, but would result in large-area chips of initially lower fabrication yield, and large-area packages consuming valuable board space. Consequently, the invention helps to alleviate the space constraint of continually shrinking applications such as cellular communications, pagers, hard disk drives, laptop computers and medical instrumentation.
Other embodiments of the invention include stacks of chips identical in function, such as a pair of DRAMs designed for flip-chip assembly by solder reflow. In these applications, portions of the leads of the metallic leadframe are formed in an undulating pattern designed to securely accommodate the solder balls for the flip chip assembly. Preferred contours are shaped to position solder balls between 0.1 and 0.5 mm diameter. In addition, the invention emphasizes the metallurgical preparation of the lead surfaces in order to promote solder wetting. A preferred surface preparation comprises selective and sequential depositions of layers of nickel and a noble metal such as palladium, or alloys thereof. In order to minimize thermomechanical stress on the solder joints, it is preferable that the size of the solder connections as well as the coefficients of thermal expansion of the various assembly components are selected based on stress modeling using finite element analysis.
The multichip assembly of the present invention has the additional benefit of reducing trace inductance by shortening conductive paths, designing conductive losses in bonding wires and solder balls approximately equal, and minimizing both. This effort is supported by sharing signals on a common conductor whenever possible. The signal path is considerably reduced compared to a simple assembly of two individual packages next to each other, just connected by conductive paths on a printed substrate or circuit board.
According to the invention, the assembly is encapsulated in a molded package. The preferred method is transfer molding using the so-called xe2x80x9c3-Pxe2x80x9d technology. Emphasis is placed on cleanliness of the molding compound by prepacking and sealing it in plastic forms which are only ruptured at time of usage, and on preventing the deleterious adhesion to the mold cavity walls of the molding compound by covering thin continuous plastic films over the mold walls.
It is an object of the present invention to provide a low-cost method and system for packaging multichip devices in thin overall package profile by disposing the leads of metallic leadframes between the chips of a stack.
Another object of the present invention is to be flexible in the multichip assembly, utilizing both wire bonding and solder reflow for connecting the chip terminals to the leads.
Another object of the present invention is to enhance production throughput by more precisely positioning solder balls in low-cost lead undulations.
Another object of the present invention is to improve product quality by promoting solder wetting and maintaining a temperature difference between wire bonding and solder reflow.
Another object of the invention is to provide reliability assurance through in-process control at no extra cost.
Another object of the invention is to introduce assembly concepts which are flexible so that they can be applied to many families of semiconductor products, and are general so that they can be applied to several future generations of products.
Another object of the invention is to minimize the cost of capital investment and to use the installed fabrication equipment base.
These objects have been achieved by the teachings of the invention concerning the modifications of metallic leads, arrangements of chip sets, and flexible assembly methods. Various modifications have been employed for the assembly and encapsulation of chip stacks.
In one embodiment of the invention, the multichip assembly comprises a stack of two chips. The bond pads of the first chip are disposed around the periphery of the chip; the pads are connected to the first surface of the leads of the leadframe by bond wires. The bond pads of the second chip are connected to the second surface of the leads by solder ball reflow.
In another embodiment of the invention, the multichip assembly comprises also a stack of two chips. The bond pads of the first chip are disposed along the center line of the chip; the pads are connected to the second surface of the leads of the leadframe by bond wires. The bond pads of the second chip are also connected to the second surface of the leads, yet by solder ball reflow.
In yet another embodiment of the invention, both chips of a stack of two chips are connected to the leads by solder ball reflow. However, the leads are fabricated in an undulated fashion so that the solder balls of the chips can be securely positioned, thus simplifying the multichip assembly and improving manufacturing yield. Moreover, metal layers are deposited onto the base material of the leadframe in order to promote solder wetting.
In all embodiments mentioned, the assemblies are encapsulated in molded packages. The mold compound not only protects the bond wires, but concurrently acts as a stress-absorbing underfill for the solder joints.
The technical advances represented by the invention, as well as the objects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.